Test driver module, Test driver module –14 – Altera Arria V Hard IP for PCI Express User Manual

Page 236

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17–14

Chapter 17: Testbench and Design Example

Test Driver Module

Arria V Hard IP for PCI Express

December 2013

Altera Corporation

User Guide

Each descriptor provides the hardware information on one DMA transfer.

Table 17–10

describes each descriptor field.

Test Driver Module

The BFM driver module, altpcietb_bfm_driver_chaining.v is configured to test the
chaining DMA example Endpoint design. The BFM driver module configures the
Endpoint Configuration Space registers and then tests the example Endpoint chaining
DMA channel. This file is stored in the
<working_dir>testbench/<variation_name>/simulation/submodules directory.

The BFM test driver module performs the following steps in sequence:

1. Configures the Root Port and Endpoint Configuration Spaces, which the BFM test

driver module does by calling the procedure

ebfm_cfg_rp_ep

, which is part of

altpcietb_bfm_configure

.

2. Finds a suitable BAR to access the example Endpoint design Control Register

space. Either BARs 2 or 3 must be at least a 256-byte memory BAR to perform the
DMA channel test. The

find_mem_bar

procedure in the

altpcietb_bfm_driver_chaining

does this.

Table 17–10. Chaining DMA Descriptor Fields

Descriptor Field

Endpoint

Access

RC Access

Description

Endpoint Address

R

R/W

A 32-bit field that specifies the base address of the memory transfer on the
Endpoint site.

RC Address

Upper DWORD

R

R/W

Specifies the upper base address of the memory transfer on the RC site.

RC Address

Lower DWORD

R

R/W

Specifies the lower base address of the memory transfer on the RC site.

DMA Length

R

R/W

Specifies the number of DMA DWORDs to transfer.

EPLAST_ENA

R

R/W

This bit is

OR

’d with the

EPLAST_ENA

bit of the control register. When

EPLAST_ENA

is set, the Endpoint DMA module updates the EPLAST field of

the descriptor table with the number of the last completed descriptor, in the
form <0 – n>. (Refer to

Table 17–7

.)

MSI_ENA

R

R/W

This bit is

OR

’d with the

MSI

bit of the descriptor header. When this bit is set

the Endpoint DMA module sends an interrupt when the descriptor is
completed.

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