Altera Arria V Hard IP for PCI Express - Manual (Page 92)

6–18 Chapter 6: IP Core Architecture
Avalon-MM Bridge TLPs
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
2. System software programs BAR1:0 to have a base address of
0x00001234 56789000
3. A TLP received with address 0x00001234 56789870
4. The upper 52 bits (0x0000123456789) are used in the BAR matching process, so this
request matches.
5. The lower 12 bits, 0x870, are passed through as the Avalon address on the
Rxm_BAR0 Avalon-MM Master port. The BAR matching software replaces the
upper 20 bits of the address with the Avalon-MM base address.
Minimizing BAR Sizes and the PCIe Address Space
For designs that include multiple BARs, you may need to modify the base address
assignments auto-assigned by Qsys in order to minimize the address space that the
BARs consume. For example, consider a Qsys system with the following components:
■ Offchip_Data_Mem DDR3 (SDRAM Controller with UniPHY) controlling 256
MBytes of memory—Qsys auto-assigned a base address of 0x00000000
■ Quick_Data_Mem (On-Chip Memory (RAM or ROM)) of 4 KBytes—Qsys
auto-assigned a base address of 0x10000000
■ Instruction_Mem (On-Chip Memory (RAM or ROM)) of 64 KBytes—Qsys
auto-assigned a base address of 0x10020000
■ PCIe (Avalon-MM Arria V Hard IP for PCI Express)
■ Cra (Avalon-MM Slave)—auto assigned base address of 0x10004000
■ Rxm_BAR0 connects to Offchip_Data_Mem DDR3 avl
■ Rxm_BAR2 connects to Quick_Data_Mem s1
■ Rxm_BAR4 connects to PCIe. Cra Avalon-MM Slave
■ Nios2 (Nios ® II Processor)
■ data_master connects to PCIe Cra, Offchip_Data_Mem DDR3 avl,
Quick_Data_Mem s1 , Instruction_Mem s1, Nios2 jtag_debug_module
■ instruction_master connects to Instruction_Mem s1