Altera Arria V Hard IP for PCI Express - Manual (Page 109)

Chapter 7: IP Core Interfaces 7–11
Arria V Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Figure 7–9 illustrates back-to-back transmission on the 64-bit Avalon-ST RX interface
with no idle cycles between the assertion of rx_st_eop and rx_st_sop .
Data Alignment and Timing for the 128-Bit Avalon-ST RX Interface
Figure 7–10 shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs
for TLPs with a three dword header and qword aligned addresses.
Figure 7–9. 64-Bit Avalon-ST Interface Back-to-Back Receive TLPs
coreclkout
rx_st_data[63:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
C. C. C. C. CCCC008347890. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C. C.
Figure 7–10. 128-Bit Avalon-ST rx_st_data <n> Cycle Definition for 3-Dword Header TLP with Qword Aligned Address
coreclkout
rx_st_valid
rx_st_data[127:96]
rx_st_data[95:64]
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_bar[7:0]
rx_st_sop
rx_st_eop
rx_st_empty
data3
header2 data2
header1 data1 data<n>
header0 data0 data<n-1>
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