Altera Arria V Hard IP for PCI Express - Manual (Page 222)

16–2 Chapter 16: SDC Timing Constraints
SDC Constraints for the Example Design
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
SDC Constraints for the Example Design
The Transceiver Reconfiguration Controller IP Core is included in the example design.
The .sdc file includes constraints for the Transceiver Reconfiguration Controller IP
Core. You may need to change the frequency and actual clock pin name to match your
design.
The .sdc file also specifies some false timing paths for Transceiver Reconfiguration
Controller and Transceiver PHY Reset Controller IP Cores. Be sure to include these
constraints in your .sdc file.