Altera Arria V Hard IP for PCI Express - Manual (Page 112)

7–14 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 7–15 illustrates back-to-back transmission on the 128-bit Avalon-ST RX
interface with no idle cycles between the assertion of rx_st_eop and rx_st_sop .
Figure 7–16 illustrates a two-cycle packet with valid data in the lower qword
( rx_st_data[63:0] ) and a one-cycle packet where the rx_st_sop and rx_st_eop occur
in the same cycle.
f For a complete description of the TLP packet header formats, refer to Appendix A,
Transaction Layer Packet (TLP) Header Formats .
Figure 7–15. 128-Bit Avalon-ST Interface Back-to-Back Receive TLPs
coreclkout
rx_st_data[127:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
rx_st_err
.. BB . BB . BB . BB . BB . BB . BB . BB . BB . BB . BB . BB . BB .
Figure 7–16. 128-Bit Packet Example Use of rx_st_empty and Single-Cycle Packet
coreclkout
rx_st_data[127:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
0000090 . 1C0020000F00000001000044329CF300 1C0020000F45612CCFA2003451009...