Configuration space, Data link layer, Configuration space –7 – Altera Arria V Hard IP for PCI Express User Manual
Page 81: Data link layer –7
Chapter 6: IP Core Architecture
6–7
Protocol Layers
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
2. The Application Layer requests permission to transmit a TLP. The Application
Layer must provide the transaction and must be prepared to provide the entire
data payload in consecutive cycles.
3. The Transaction Layer verifies that sufficient flow control credits exist and
acknowledges or postpones the request.
4. The Transaction Layer forwards the TLP to the Data Link Layer.
Configuration Space
The Configuration Space implements the following Configuration Space Registers
and associated functions:
■
Header Type 0 Configuration Space for Endpoints
■
Header Type 1 Configuration Space for Root Ports
■
MSI Capability Structure
■
MSI-X Capability Structure
■
PCI Power Management Capability Structure
■
PCI Express Capability Structure
■
SSID / SSVID Capability Structure
■
Virtual Channel Capability Structure
■
Advance Error Reporting Capability Structure
The Configuration Space also generates all messages (PME#, INT, error, slot power
limit), MSI requests, and completion packets from configuration requests that flow in
the direction of the root complex, except slot power limit messages, which are
generated by a downstream port. All such transactions are dependent upon the
content of the PCI Express Configuration Space as described in the
Refer To
“Configuration Space Register Content” on page 8–1
for the complete content of these registers.
Data Link Layer
The Data Link Layer is located between the Transaction Layer and the Physical Layer.
It maintains packet integrity and communicates (by DLL packet transmission) at the
PCI Express link level (as opposed to component communication by TLP
transmission in the interconnect fabric).
The DLL implements the following functions:
■
Link management through the reception and transmission of DLL packets (DLLP),
which are used for the following functions:
■
For power management of DLLP reception and transmission
■
To transmit and receive
ACK
/
NACK
packets
■
Data integrity through generation and checking of CRCs for TLPs and DLLPs
■
TLP retransmission in case of
NAK
DLLP reception using the retry buffer