Altera Arria V Hard IP for PCI Express - Manual (Page 276)

18–6 Chapter 18: Debugging
Recommended Reset Sequence to Avoid Link Training Issues
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
f For more information about SignalTap, refer to the Design Debugging Using the
SignalTap II Embedded Logic Analyzer chapter in volume 3 of the Quartus II Handbook.
Recommended Reset Sequence to Avoid Link Training Issues
Successful link training can only occur after the FPGA is configured and the
Transceiver Reconfiguration Controller IP Core has dynamically reconfigured
SERDES analog settings to optimize signal quality. For designs using CvP, link
training occurs after configuration of the I/O ring and Hard IP for PCI Express IP
Core.
Figure 9–1 on page 9–2 shows the key signals that reset, control dynamic
reconfiguration, and link training. Successful reset sequence includes the following
steps:
1. Wait until the FPGA is configured as indicated by the assertion of CONFIG_DONE
from the reconfig block controller.
2. Deassert the mgmt_rst_reset input to the Transceiver Reconfiguration Controller
IP Core.
3. Wait for tx_cal_busy and rx_cal_busy SERDES outputs to be deasserted.
4. Deassert pin_perstn to take the Hard IP for PCIe out of reset. For plug-in cards,
the minimum assertion time for pin_perstn is 100 ms. Embedded systems do not
have a minimum assertion time for pin_perstn .
5. Wait for the reset_status output to be deasserted.
6. Deassert the reset output to the Application Layer.
Setting Up Simulation
Changing the simulation parameters reduces simulation time and provides greater
visibility. Depending on the variant you are simulating, the following changes may be
useful when debugging:
■ Changing Between Serial and PIPE Simulation
■ Use the PIPE Interface for Gen1 and Gen2 Variants
■ Reduce Counter Values for Serial Simulations
■ Disable the Scrambler for Gen1 and Gen2 Simulations
Changing Between Serial and PIPE Simulation
By default, the Altera testbench runs a serial simulation. You can change between
serial and PIPE simulation by editing the top-level testbench file.
The hip_ctrl_simu_mode_pipe signal and the enable_pipe32_sim_hwtcl parameter
specify serial or PIPE simulation. When both are set to 1'b0, the simulation runs in
serial mode. When both are set to1'b1, the simulation runs in PIPE mode.
Complete the following steps to enable the 32-bit Gen3 PIPE simulation. These steps
assume that you are running the Gen1 ×4 testbench: