Altera Arria V Hard IP for PCI Express - Manual (Page 17)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
2. Getting Started with the Arria Hard IP
for PCI Express
Getting Started with the Arria Hard IP for PCI Express
This section provides step-by-step instructions to help you quickly customize,
simulate, and compile the Arria Hard IP for PCI Express using either the
MegaWizard Plug-In Manager or Qsys design flow. When you install the Quartus II
software you also install the IP Library. This installation includes design examples for
Hard IP for PCI Express in <install_dir>/ip/altera/altera_pcie/
altera_pcie_hip_ast_ed/example_design/
<device> directory.
1
If you have an existing Arria 12.1 or older design, you must regenerate it in 13.1
before compiling with the 13.1 version of the Quartus II software.
After you install the Quartus II software for 13.1, you can copy the design examples
from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/
example_design/
<device> directory. This walkthrough uses the Gen1 ×4 Endpoint.
The following figure illustrates the top-level modules of the testbench in which the
DUT, a Gen1 ×4 Endpoint, connects to a chaining DMA engine, labeled APPS in the
following figure, and a Root Port model. The Transceiver Reconfiguration Controller
dynamically reconfigures analog settings to optimize signal quality of the serial
interface. The pcie_reconfig_driver drives the Transceiver Reconfiguration Controller.
The simulation can use the parallel PHY Interface for PCI Express (PIPE) or serial
interface.
For a detailed explanation of this example design, refer to Chapter 18, Testbench and
Design Example . If you choose the parameters specified in this chapter, you can run
all of the tests included in Chapter 18 .
Figure 2–1. Testbench for an Endpoint
L
APPS
altpcied_sv_hwtcl.v
Stratix V Hard IP for PCI Express Testbench for Endpoints
Avalon-ST TX
Avalon-ST RX
reset
status
Avalon-ST TX
Avalon-ST RX
reset
status
DUT
altpcie_sv_hip_ast_hwtcl.v
Root Port Model
altpcie_tbed_sv_hwtcl.v
PIPE or
Serial
Interface
Root Port BFM
altpcietb_bfm_rpvar_64b_x8_pipen1b
Root Port Driver and Monitor
altpcietb_bfm_vc_intf
December 2013
UG-01110-1.5