Altera Arria V Hard IP for PCI Express - Manual (Page 135)

Chapter 7: IP Core Interfaces 7–37
Arria V Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
f
Refer to the PCI Local Bus Specification for descriptions of the Control registers.
Table 7–15 describes the use of the various fields of the Configuration MSI Control
and Status Register.
cfg_msi_data 16 O cfg_msi_data[15:0] is message data for MSI.
Table 9–4 on
page 9–3
0x050
cfg_busdev 13 O
Bus/Device Number captured by or programmed in the
Hard IP.
Table A–5 on
page A–2
0x08
Table 7–14. Configuration Space Register Descriptions (Part 4 of 4)
Register Width Dir Description
Register
Reference
Table 7–15. Configuration MSI Control Register Field Descriptions
Bit(s) Field Description
[15:9] reserved —
[8]
mask
capability
Per vector masking capable. This bit is hardwired to 0 because the functions do not
support the optional MSI per vector masking using the
Mask_Bits and
Pending_Bits registers defined in the PCI Local Bus Specification, Rev. 3.0 . Per
vector masking can be implemented using Application Layer registers.
[7]
64-bit
address
capability
64-bit address capable
■ 1: function capable of sending a 64-bit message address
■ 0: function not capable of sending a 64-bit message address
[6:4]
multiples
message
enable
Multiple message enable: This field indicates permitted values for MSI signals. For
example, if “100” is written to this field 16 MSI signals are allocated
■ 000: 1 MSI allocated
■ 001: 2 MSI allocated
■ 010: 4 MSI allocated
■ 011: 8 MSI allocated
■ 100: 16 MSI allocated
■ 101: 32 MSI allocated
■ 110: Reserved
■ 111: Reserved
[3:1]
multiple
message
capable
Multiple message capable: This field is read by system software to determine the
number of requested MSI messages.
■ 000: 1 MSI requested
■ 001: 2 MSI requested
■ 010: 4 MSI requested
■ 011: 8 MSI requested
■ 100: 16 MSI requested
■ 101: 32 MSI requested
■ 110: Reserved
[0] MSI Enable If set to 0, this component is not permitted to use MSI.