Ip core interfaces, Chapter 7. ip core interfaces – Altera Arria V Hard IP for PCI Express User Manual

Page 99

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December 2013

Altera Corporation

Arria V Hard IP for PCI Express

User Guide

7. IP Core Interfaces

This chapter describes the signals that are part of the Arria V Hard IP for PCI Express
IP core. It describes the top-level signals in the following IP cores:

■

Arria V Hard IP for PCI Express

■

Avalon-MM Hard IP for PCI Express

Variants using the Avalon-ST interface are available in both the MegaWizard Plug-In
Manager and the Qsys design flows. Variants using the Avalon-MM interface are only
available in the Qsys design flow. Variants using the Avalon-ST interfaces offer a
richer feature set; however, if you are not familiar with the PCI Express protocol,
variants using the Avalon-MM interface may be easier to understand. The
Avalon-MM variants include a PCI Express to Avalon-MM bridge that translates the
PCI Express read, write and completion Transaction Layer Packets (TLPs) into
standard Avalon-MM read and write commands typically used by master and slave
interfaces to access memories and registers. Consequently, you do not need a detailed
understanding of the PCI Express TLPs to use the Avalon-MM variants. Refer to

“Differences in Features Available Using the Avalon-MM and Avalon-ST Interfaces”
on page 1–2

to learn about the difference in the features available for the Avalon-ST

and Avalon-MM interfaces.

Because the Arria V Hard IP for PCI Express offers exactly the same feature set in the
MegaWizard Plug-In Manager and Qsys design flows, your decision about which
design flow to use depends on whether you want to integrate the Arria V Hard IP for
PCI Express using RTL instantiation or Qsys. The Qsys system integration tool
automatically generates the interconnect logic between the IP components in your
system, saving time and effort. Refer to

“MegaWizard Plug-In Manager Design Flow”

on page 2–3

and

“Qsys Design Flow” on page 2–10

for a description of the steps

involved in the two design flows.

Table 7–1

lists each interface and provides a link to the subsequent sections that

describe each signal. The signals are described in the order in which they are shown in

Figure 7–2

Table 7–1. Signal Groups in the Arria V Hard IP for PCI Express (Part 1 of 2)

Signal Group