Altera Arria V Hard IP for PCI Express - Manual (Page 224)

17–2 Chapter 17: Testbench and Design Example
Endpoint Testbench
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
■ It can only handle received read requests that are less than or equal to the
currently set Maximum payload size option specified under PCI Express/PCI
Capabilites
heading under the Device tab using the parameter editor. Many
systems are capable of handling larger read requests that are then returned in
multiple completions.
■ It always returns a single completion for every read request. Some systems split
completions on every 64-byte address boundary.
■ It always returns completions in the same order the read requests were issued.
Some systems generate the completions out-of-order.
■ It is unable to generate zero-length read requests that some systems generate as
flush requests following some write transactions. The Application Layer must be
capable of generating the completions to the zero length read requests.
■ It uses fixed credit allocation.
■ It does not support parity.
■ It does not support multi-function designs.
Endpoint Testbench
After you install the Quartus II software for 11.1, you can copy any of the five example
designs from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed
/example_design
directory. You can generate the testbench from the example design
as was shown in Chapter 2, Getting Started with the Arria Hard IP for PCI Express .
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces
of the Root Port and Endpoints or the serial PCI Express interface. The testbench
design does not allow more than one PCI Express link to be simulated at a time.
Figure 17–1 presents a high level view of the design example.
The top-level of the testbench instantiates four main modules:
Figure 17–1. Design Example for Endpoint Designs
APPS
altpcied_sv_hwtcl.v
Hard IP for PCI Express Testbench for Endpoints
Avalon-ST TX
Avalon-ST RX
reset
status
Avalon-ST TX
Avalon-ST RX
reset
status
DUT
altpcie_sv_hip_ast_hwtcl.v
Root Port Model
altpcie_tbed_sv_hwtcl.v
PIPE or
Serial
Interface
Root Port BFM
altpcietb_bfm_rpvar_64b_x4_pipen1b
Root Port Driver and Monitor
altpcietb_bfm_vc_intf