Altera Arria V Hard IP for PCI Express - Manual (Page 225)

Chapter 17: Testbench and Design Example 17–3
Root Port Testbench
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
■ <qsys_systemname>— This is the example Endpoint design. For more
information about this module, refer to
“Chaining DMA Design Examples” on
page 17–4 .
■ altpcietb_bfm_top_rp.v —This is the Root Port PCI Express BFM. For more
information about this module, refer to “Root Port BFM” on page 17–20 .
■ altpcietb_pipe_phy —There are eight instances of this module, one per lane. These
modules interconnect the PIPE MAC layer interfaces of the Root Port and the
Endpoint. The module mimics the behavior of the PIPE PHY layer to both MAC
interfaces.
■ altpcietb_bfm_driver_chaining —This module drives transactions to the Root
Port BFM. This is the module that you modify to vary the transactions sent to the
example Endpoint design or your own design. For more information about this
module, refer to
“Root Port Design Example” on page 17–18 .
In addition, the testbench has routines that perform the following tasks:
■ Generates the reference clock for the Endpoint at the required frequency.
■ Provides a PCI Express reset at start up.
1 One parameter, serial_sim_hwtcl , in the altprice_tbed_sv_hwtcl.v file, controls
whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the
simulation runs in PIPE mode; when set to 1, it runs in serial mode.
Root Port Testbench
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces
of the Root Port and Endpoints or the serial PCI Express interface. The testbench
design does not allow more than one PCI Express link to be simulated at a time. The
top-level of the testbench instantiates four main modules:
■ <qsys_systemname>— Name of Root Port This is the example Root Port design. For
more information about this module, refer to
“Root Port Design Example” on
page 17–18 .
■ altpcietb_bfm_ep_example_chaining_pipen1b —This is the Endpoint PCI
Express mode described in the section “Chaining DMA Design Examples” on
page 17–4 .
■ altpcietb_pipe_phy —There are eight instances of this module, one per lane. These
modules connect the PIPE MAC layer interfaces of the Root Port and the Endpoint.
The module mimics the behavior of the PIPE PHY layer to both MAC interfaces.
■ altpcietb_bfm_driver_rp —This module drives transactions to the Root Port BFM.
This is the module that you modify to vary the transactions sent to the example
Endpoint design or your own design. For more information about this module, see
“Test Driver Module” on page 17–14 .
The testbench has routines that perform the following tasks:
■ Generates the reference clock for the Endpoint at the required frequency.
■ Provides a reset at start up.