Altera Arria V Hard IP for PCI Express - Manual (Page 201)

Chapter 11: Interrupts 11–7
Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Enabling MSI or Legacy Interrupts
The PCI Express Avalon-MM bridge selects either MSI or legacy interrupts
automatically based on the standard interrupt controls in the PCI Express
Configuration Space registers. Software can write the
Interrupt Disable bit, which is
bit 10 of the Command register (at Configuration Space offset 0x4) to disable legacy
interrupts. Software can write the MSI Enable bit, which is bit 0 of the MSI Control
Status register in the MSI capability register (bit 16 at configuration space offset
0x50), to enable MSI interrupts.
Software can only enable one type of interrupt at a time. However, to change the
selection of MSI or legacy interrupts during operation, software must ensure that no
interrupt request is dropped. Therefore, software must first enable the new selection
and then disable the old selection. To set up legacy interrupts, software must first
clear the
Interrupt Disable bit and then clear the MSI enable bit. To set up MSI
interrupts, software must first set the MSI enable bit and then set the Interrupt
Disable bit.
Generation of Avalon-MM Interrupts
Generation of Avalon-MM interrupts requires the instantiation of the CRA slave
module where the interrupt registers and control logic are implemented. The CRA
slave port has an Avalon-MM Interrupt,
CRAIrq_o , output signal. A write access to an
Avalon-MM mailbox register sets one of the P2A_MAILBOX_INT<n> bits in the “PCI
Express to Avalon-MM Interrupt Status Register for Endpoints 0x3060” on
page 8–21
and asserts the, if enabled. Software can enable the interrupt by writing to
the “INT-X Interrupt Enable Register for Endpoints 0x3070” on page 8–21 through the
CRA slave. After servicing the interrupt, software must clear the appropriate serviced
interrupt
status bit in the PCI-Express-to-Avalon-MM Interrupt Status register and
ensure that there is no other interrupt pending.
Interrupts for End Points Using the Avalon-MM Interface with Multiple
MSI/MSI-X Support
If you select Enable multiple MSI/MSI-X support under the Avalon-MM System
Settings
banner in the GUI, the Hard IP for PCI Express exports the MSI, MSI-X, and
INTx interfaces to the Application Layer. The Application Layer must include a
Custom Interrupt Handler to send interrupts to the Root Port. You must design this
Custom Interrupt Handler.
Figure 11–6 provides a an overview of the logic for the
Custom Interrupt Handler. The Custom Interrupt Handler should include hardware
to perform the following tasks:
■ An MSI/MXI-X IRQ Avalon-MM Master port to drive MSI or MSI-X interrupts as
memory writes to the PCIe Avalon-MM Bridge.
■ A legacy interrupt signal, IntxReq_i , to drive legacy interrupts from the
MSI/MSI-X IRQ module to the Hard IP for PCI Express.
■ An MSI/MSI-X Avalon-MM Slave port to receive interrupt control and status from
the PCIe Root Port.