Altera Arria V Hard IP for PCI Express - Manual (Page 53)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
4. Parameter Settings for the Arria V
Hard IP for PCI Express
This chapter describes the parameters which you can set using the MegaWizard
Plug-In Manager or Qsys design flow to instantiate a Arria V Hard IP for PCI Express
IP core. The appearance of the GUI is identical for the two design flows.
1
In the following tables, hexadecimal addresses in green are links to additional
information in the “Register Descriptions” chapter.
System Settings
The first group of settings defines the overall system. Table 4–1 describes these
settings.9
Table 4–1. System Settings for PCI Express (Part 1 of 3)
Parameter Value Description
Number of Lanes ×1, ×2, ×4, ×8 Specifies the maximum number of lanes supported.
Lane Rate
Gen1 (2.5 Gbps)
Gen2 (2.5/5.0 Gbps)
Specifies the maximum data rate at which the link can operate.Arria V
supports Gen1 ×1, ×2, ×4, ×8 and Gen2 ×1, ×2, and ×4
Port type
Native Endpoint
Root Port
Legacy Endpoint
Specifies the function of the port. Altera recommends Native Endpoint
for all new Endpoint designs. Select Legacy Endpoint only when you
require I/O transaction support for compatibility.
The Endpoint stores parameters in the Type 0 Configuration Space which
is outlined in
Table 8–2 on page 8–2 . The Root Port stores parameters in
the Type 1 Configuration Space which is outlined n Table 8–3 on
page 8–2 .
Application Interface
64-bit Avalon-ST
128-bit Avalon-ST
Specifies the interface between the PCI Express Transaction Layer and
the Application Layer. Refer to
Table 9–2 on page 9–6 for a
comprehensive list of available link width, interface width, and frequency
combinations.
December 2013
UG-01110-1.5