Altera Arria V Hard IP for PCI Express - Manual (Page 33)

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–17
Compiling the Design in the Qsys Design Flow
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
14. Add the Synopsys Design Constraint (SDC) shown in Example 2–3 , to the top-level
design file for your Quartus II project.
15. To compile your design using the Quartus II software, on the Processing menu,
click Start Compilation. The Quartus II software then performs all the steps
necessary to compile your design.
Example 2–3. Synopsys Design Constraint
create_clock -period “100 MHz” -name {refclk_pci_express} {*refclk_*}
derive_pll_clocks
derive_clock_uncertainty
######################################################################
# PHY IP reconfig controller constraints
# Set reconfig_xcvr clock
# Modify to match the actual clock pin name
# used for this clock, and also changed to have the correct period set
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}
{*reconfig_xcvr_clk*}
######################################################################
# HIP Soft reset controller SDC constraints
set_false_path -to [get_registers
*altpcie_rs_serdes|fifo_err_sync_r[0]]
set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to
[get_registers *altpcie_rs_serdes|*]
# Hard IP testin pins SDC constraints
set_false_path -from [get_pins -compatibilitly_mode *hip_ctrl*]