Altera Arria V Hard IP for PCI Express - Manual (Page 66)

5–2 Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express
Base Address Registers
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Base Address Registers
Table 5–2 describes the Base Address (BAR) register parameters.
RX Buffer credit
allocation -
performance for
received requests
(continued)
Minimum
Low
Balanced
High
Maximum
■ Balanced–This setting allocates approximately half the RX Buffer
space to received requests and the other half of the RX Buffer space
to received completions. Select this option for variations where the
received requests and received completions are roughly equal.
■ High–This setting configures most of the RX Buffer space for
received requests and allocates a slightly larger than minimum
amount of space for received completions. Select this option when
most of the PCIe requests are generated by the other end of the PCIe
link and the local application layer logic only infrequently generates a
small burst of read requests. This option is recommended for typical
root port applications where most of the PCIe traffic is generated by
DMA engines located in the endpoints.
■ Maximum–This setting configures the minimum PCIe specification
allowed amount of completion space, leaving most of the RX Buffer
space for received requests. Select this option when most of the PCIe
requests are generated by the other end of the PCIe link and the local
Application Layer never or only infrequently generates single read
requests. This option is recommended for control and status
endpoint applications that do not generate any PCIe requests of their
own and only are the target of write and read requests from the Root
Complex.
Reference clock
frequency 100 MHz
125 MHz
The PCI Express Base Specification 2.1 requires a
100 MHz
±
300 ppm reference clock. The 125 MHz reference clock is
provided as a convenience for systems that include a 125 MHz clock
source.
Use 62.5 MHz
Application Layer
clock
On/Off This is a special power saving mode available only for Gen1 ×1 variants.
Enable configuration
via the PCIe link
On/Off
When On, the Quartus II software places the Endpoint in the location
required for configuration via protocol (CvP).
Table 5–1. System Settings for PCI Express (Part 2 of 2)
Parameter Value Description
Table 5–2. BARs and Expansion ROM
Parameter Value Description
Type
0x010 , 0x014 ,
0x018 , 0x01C ,
0x020 , 0x024
64-bit prefetchable memory
32-bit non-prefetchable memory
Not used
If you select 64-bit prefetchable memory, 2 contiguous BARs are
combined to form a 64-bit prefetchable BAR; you must set the
higher numbered BAR to Disabled. A non-prefetchable 64-bit BAR
is not supported because in a typical system, the Root Port Type 1
Configuration Space sets the maximum non-prefetchable memory
window to 32-bits. The BARs can also be configured as separate
32-bit non-prefetchable memories.
Size 16 Bytes–8 EBytes
Specifies the number of address bits required for address
translation. Qsys automatically calculates the BAR Size based on the
address range specified in your Qsys system. You cannot change
this value.