Altera Arria V Hard IP for PCI Express - Manual (Page 199)

Chapter 11: Interrupts 11–5
Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
The Root Error Status register reports the status of error messages. The Root Error
Status register is part of the PCI Express AER Extended Capability structure. It is
located at offset 0x830 of the Configuration Space registers.
Interrupts for Endpoints Using the Avalon-MM Interface to the
Application Layer
The PCI Express Avalon-MM bridge supports MSI or legacy interrupts. The completer
only single dword variant includes an interrupt generation module. For other variants
with the Avalon-MM interface, interrupt support requires instantiation of the CRA
slave module where the interrupt registers and control logic are implemented.
The PCI Express Avalon-MM bridge supports the Avalon-MM individual requests
interrupt scheme: multiple input signals indicate incoming interrupt requests, and
software must determine priorities for servicing simultaneous interrupts the
Avalon-MM Arria V Hard IP for PCI Express receives.
The RX master module port has as many as 16 Avalon-MM interrupt input signals
(
RXmirq_irq[ <n> :0] , where <n> < 16)) . Each interrupt signal indicates a distinct
interrupt source. Assertion of any of these signals, or a PCI Express mailbox register
write access, sets a bit in the PCI Express interrupt status register. Multiple bits can be
set at the same time; software determines priorities for servicing simultaneous
incoming interrupt requests. Each set bit in the PCI Express interrupt status register
generates a PCI Express interrupt, if enabled, when software determines its turn.
Software can enable the individual interrupts by writing to the “INT-X Interrupt
Enable Register for Endpoints 0x3070” on page 8–21 through the CRA slave.
When any interrupt input signal is asserted, the corresponding bit is written in the
“Avalon-MM to PCI Express Interrupt Status Register 0x0040” on page 8–12 .
Software reads this register and decides priority on servicing requested interrupts.
After servicing the interrupt, software must clear the appropriate serviced interrupt
status bit and ensure that no other interrupts are pending. For interrupts caused by
“Avalon-MM to PCI Express Interrupt Status Register 0x0040” on page 8–12 mailbox
writes, the status bits should be cleared in the “Avalon-MM to PCI Express Interrupt
Status Register 0x0040” on page 8–12 . For interrupts due to the incoming interrupt
signals on the Avalon-MM interface, the interrupt status should be cleared in the
Avalon-MM component that sourced the interrupt. This sequence prevents interrupt
requests from being lost during interrupt servicing.