Altera Arria V Hard IP for PCI Express - Manual (Page 278)

18–8 Chapter 18: Debugging
).Use Third-Party PCIe Analyzer
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
3. To disable the scrambler, set test_in[2] = 1 .
4. Save altpcie_tbed_sv_hwtcl.v.
Change between the Hard and Soft Reset Controller
The Hard IP for PCI Express includes both hard and soft reset control logic. By
default, Gen1 ES and Gen1 and Gen2 production devices use the Hard Reset
Controller. Gen2 and Gen3 ES devices and Gen3 production devices use the soft reset
controller. For variants that use the hard reset controller, changing to the soft reset
controller provides greater visibility.
Complete the following steps to change to the soft reset controller:
1. Open <work_dir>/<variant>/synthesis/<variant>.v.
2. Search for the string, hip_hard_reset_hwtcl .
3. If hip_hard_reset_hwtcl = 1 , the hard reset controller is active. Set
hip_hard_reset_hwtcl = 0 to change to the soft reset controller.
4. Save variant.v.
).
Use Third-Party PCIe Analyzer
A third-party logic analyzer for PCI Express records the traffic on the physical link
and decodes traffic, saving you the trouble of translating the symbols yourself. A
third-party logic analyzer can show the two-way traffic at different levels for different
requirements. For high-level diagnostics, the analyzer shows the LTSSM flows for
devices on both side of the link side-by-side. This display can help you see the link
training handshake behavior and identify where the traffic gets stuck. A traffic
analyzer can display the contents of packets so that you can verify the contents. For
complete details, refer to the third-party documentation.
BIOS Enumeration Issues
Both FPGA programming (configuration) and the initialization of a PCIe link require
time. There is some possibility that Altera FPGA including a Hard IP block for PCI
Express may not be ready when the OS/BIOS begins enumeration of the device tree.
If the FPGA is not fully programmed when the OS/BIOS begins its enumeration, the
OS does not include the Hard IP for PCI Express in its device map. To eliminate this
issue, you can do a soft reset of the system to retain the FPGA programming while
forcing the OS/BIOS to repeat its enumeration.