Altera Arria V Hard IP for PCI Express - Manual (Page 125)

Chapter 7: IP Core Interfaces 7–27
Arria V Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
ECC Error Signals
Table 7–7 describes the ECC error signals. When a correctable ECC error occurs, the
Arria V Hard IP for PCI Express recovers without any loss of information. No
Application Layer intervention is required. In the case of uncorrectable ECC error, the
data in retry buffer is cleared. Altera recommends that you reset the Hard IP for PCI
Express IP Core.
Interrupts for Endpoints
Table 7–8 describes the IP core’s interrupt signals for Endpoints. These signals are
level sensitive. Refer to Chapter 11, Interrupts for descriptions of all interrupt
mechanisms.
Table 7–7. ECC Error Signals for Hard IP Implementation (1)
Signal I/O Description
derr_cor_ext_rcv0 O
Indicates a corrected error in the RX buffer. This signal is for debug only. It
is not valid until the RX buffer is filled with data. This is a pulse, not a level,
signal. Internally, the pulse is generated with the 250 MHz clock. A pulse
extender extends the signal so that the FPGA fabric running at 125 MHz
can capture it. Because the error was corrected by the IP core, no
Application Layer intervention is required.
(2)
derr_rpl O
Indicates an uncorrectable error in the retry buffer. This signal is for debug
only.
(2)
derr_cor_ext_rpl O
Indicates a corrected ECC error in the retry buffer. This signal is for debug
only. Because the error was corrected by the IP core, no Application Layer
intervention is required.
(2)
Note to Table 7–7 :
(1) The Avalon-ST rx_st_err described in Table 7–3 on page 7–5 indicates an uncorrectable error in the RX buffer.
(2) Debug signals are not rigorously verified and should only be used to observe behavior.
Table 7–8. Interrupt Signals for Endpoints (Part 1 of 2)
Signal I/O Description
app_msi_req I
Application Layer MSI request. Assertion causes an MSI posted write TLP to be generated
based on the MSI configuration register values and the tl_
app_msi_tc and app_msi_num
input ports. In Root Port mode, the core generates an MSI TLP to the Root Port over the
Avalon-ST RX interface. In this case, the header bit[127] of
rx_st_data is set to 1 to
indicate that the TLP being forwarded to the Application Layer was generated in response
to an assertion of the
app_msi_req pin; otherwise, bit[127] is set to 0.
app_msi_ack O
Application Layer MSI acknowledge. This signal acknowledges the Application Layer's
request for an MSI interrupt.
app_msi_tc[2:0] I
Application Layer MSI traffic class. This signal indicates the traffic class used to send the
MSI (unlike INTX interrupts, any traffic class can be used to send MSIs).
app_msi_num[4:0] I
MSI number of the Application Layer. This signal provides the low order message data
bits to be sent in the message data field of MSI messages requested by tl_
app_msi_req .
Only bits that are enabled by the MSI Message Control register apply. Refer to Table 7–15
on page 7–37 for more information.