Altera Arria V Hard IP for PCI Express - Manual (Page 170)

8–16 Chapter 8: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Access Content
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Root Port TLP Data Registers
The TLP data registers provide a mechanism for the Application Layer to specify data
that the Root Port uses to construct Configuration TLPs, Message TLPs, I/O TLPs,
and single dword Memory Reads and Write requests. The Root Port then drives the
TLPs on the TLP Direct Channel to access the Configuration Space, I/O space, or
Endpoint memory.
Figure 8–1 illustrates these registers.
Figure 8–1. Root Port TLP Data Registers
RX_TX_CNTL
RP_RXCPL_
REG0
RP_RXCPL_
REG
RP_RXCPL_
STATUS
Control
Register
Access
Slave
Avalon-MM
Master
32
32
32
32
64
64
32
IRQ
RP TX
CTRL
TX
CTRL
RP_TX_FIFO
RP CPL
CTRL
RX
CTRL
RP_RXCPL_FIFO
TLP Direct Channel
to Hard IP for PCIe
Root-Port TLP Data Registers Avalon-MM Bridge -
RX_TX_Reg1
RP_TX_Reg0