Altera Arria V Hard IP for PCI Express - Manual (Page 54)

4–2 Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express
System Settings
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
RX Buffer credit
allocation -
performance for
received requests
Minimum
Low
Balanced
High
Maximum
Determines the allocation of posted header credits, posted data credits,
non-posted header credits, completion header credits, and completion
data credits in the 6 KByte RX buffer. The 5 settings allow you to adjust
the credit allocation to optimize your system. The credit allocation for
the selected setting displays in the message pane.
Refer to Chapter 13, Flow Control , for more information about
optimizing performance. The Flow Control chapter explains how the RX
credit allocation and the Maximum payload size that you choose affect
the allocation of flow control credits. You can set the Maximum payload
size parameter in
Table 4–2 on page 4–4 .
■ Minimum–This setting configures the minimum PCIe specification
allowed for non-posted and posted request credits, leaving most of
the RX Buffer space for received completion header and data. Select
this option for variations where application logic generates many read
requests and only infrequently receives single requests from the PCIe
link.
■ Low– This setting configures a slightly larger amount of RX Buffer
space for non-posted and posted request credits, but still dedicates
most of the space for received completion header and data. Select
this option for variations where application logic generates many read
requests and infrequently receives small bursts of requests from the
PCIe link. This option is recommended for typical endpoint
applications where most of the PCIe traffic is generated by a DMA
engine that is located in the endpoint application layer logic.
■ Balanced–This setting allocates approximately half the RX Buffer
space to received requests and the other half of the RX Buffer space
to received completions. Select this option for applications where the
received requests and received completions are roughly equal.
■ High–This setting configures most of the RX Buffer space for
received requests and allocates a slightly larger than minimum
amount of space for received completions. Select this option where
most of the PCIe requests are generated by the other end of the PCIe
link and the local application layer logic only infrequently generates a
small burst of read requests. This option is recommended for typical
root port applications where most of the PCIe traffic is generated by
DMA engines located in the endpoints.
■ Maximum–This setting configures the minimum PCIe specification
allowed amount of completion space, leaving most of the RX Buffer
space for received requests. Select this option when most of the PCIe
requests are generated by the other end of the PCIe link and the local
application layer logic never or only infrequently generates single
read requests. This option is recommended for control and status
endpoint applications that don't generate any PCIe requests of their
own and only are the target of write and read requests from the root
complex.
Table 4–1. System Settings for PCI Express (Part 2 of 3)
Parameter Value Description