Altera Arria V Hard IP for PCI Express - Manual (Page 216)

14–6 Chapter 14: Error Handling
Uncorrectable and Correctable Error Status Bits
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Uncorrectable and Correctable Error Status Bits
The following section is reprinted with the permission of PCI-SIG. Copyright 2010
PCI-SIGR.
Figure 14–1 illustrates the Uncorrectable Error Status register. The default value of all
the bits of this register is 0. An error status bit that is set indicates that the error
condition it represents has been detected. Software may clear the error status by
writing a 1 to the appropriate bit.
Figure 14–2 illustrates the Correctable Error Status register. The default value of all the
bits of this register is 0. An error status bit that is set indicates that the error condition
it represents has been detected. Software may clear the error status by writing a 1 to
the appropriate bit.0
Figure 14–1. Uncorrectable Error Status Register
Rsvd Rsvd Rsvd
TLP Prefix Blocked Error Status
AtomicOp Egress Blocked Status
MC Blocked TLP Status
Uncorrectable Internal Error Status
ACS Violation Status
Unsupported Request Error Status
ECRC Error Status
Malformed TLP Status
Receiver Overflow Status
Unexpected Completion Status
Completer Abort Status
Completion Timeout Status
Flow Control Protocol Status
Poisoned TLP Status
Surprise Down Error Status
Data Link Protocol Error Status
Undefined
22 21 20 19 26 25 24 23 18 17 16 15 14 13 12 11 6 5 4 3 1 0 31
Figure 14–2. Correctable Error Status Register
Rsvd Rsvd Rsvd
Header Log Overflow Status
Corrected Internal Error Status
Advisory Non-Fatal Error Status
Replay Timer Timeout Status
REPLAY_NUM Rollover Status
Bad DLLP Status
Bad TLP Status
Receiver Error Status
16 15 14 13 12 11 9 8 7 6 5 1 0 31