Rockwell Automation 20P PowerFlex Digital DC Drive - Manual (Page 324)

324 Rockwell Automation Publication 20P-UM001I-EN-P - February 2013
Appendix D Control Block Diagrams
Speed Regulator PI Block
Speed R
egul
at
or
PI
B
lock
Σ
+
-
+ +
P99 Spd R
eg K
p O
ut
Ze
ro
T
F
Sp
eed
A
d
ap
ti
ve
and
Speed Zero Logic
F
P87 Sp
d R
eg
K
p
A
nt
i-Windup
Torque Current Limits
A
n
ti-Windup
P93 Spd R
eg K
p B
as
e
P94 Spd R
eg K
i B
as
e
Sp
ee
d
P / I Base
P459 Sp
dRe
g Kp
By
pa
ss
P460 Sp
dRe
g Ki
By
pa
ss
Σ
By
pa
ss
g
ai
ns
are u
se
d
w
he
n
P458 [SpdReg FB Bypass] = “Enabled” (1)
and the Encoder or Tachometer signal is lost, causing Armature Voltage Feedback to be used.
P188 A
da
pt
ive
P
Ga
in
1
P190 A
da
pt
ive
P
Ga
in
2
P192 A
da
pt
ive
P
Ga
in
3
P181 A
da
pt
ive
Spd
En
P117 Sp
eed
R
eg
In
Pct
P183 A
da
pt
ive
Ref
P118 Sp
eed
R
eg
In
P88 Spd Reg Ki P189 A
da
pt
ive
I Ga
in
1
P193 A
da
pt
ive
I Ga
in
3
P181 A
da
pt
ive
Spd
En
P100 Sp
d R
eg
Ki
Out
P444 Spd Reg P Filter
To S
peed
R
eg
ulator
Block Diagram PI Output
P348 Lock Speed Integ
P191 A
da
pt
ive
I Ga
in
1
(2 ms)
P1009 Sp
d R
eg
Fdbk
Pct
P1008 Sp
d R
eg
Fdbk
Σ
+
-
P1010 Spd R
eg E
rr
P1011 Sp
d R
eg
Err
Pct
P643 SpdReg AntiBckup
P7
0
A
nlg In1
Sel
P7
5
A
nlg In2
Sel
P8
0
A
nlg In3
Sel
P7
82
PID Target P1
210
W Target
P181 A
da
pt
ive
Spd
En
P182 A
da
pt
ive
Reg
Type