Document Outline

• Arria V Hard IP for PCI Express User Guide
  • Contents
  • 1. Datasheet
    • Features
    • Release Information
    • Device Family Support
    • Configurations
    • Debug Features
    • IP Core Verification
    • Performance and Resource Utilization
    • Recommended Speed Grades
  • 2. Getting Started with the Arria Hard IP for PCI Express
    • Getting Started with the Arria Hard IP for PCI Express
    • MegaWizard Plug-In Manager Design Flow
    • Customizing the Endpoint in the MegaWizard Plug-In Manager Design Flow
      • Understanding the Files Generated
    • Qsys Design Flow
      • Generating the Testbench
      • Understanding the Files Generated
      • Simulating the Example Design
      • Understanding Channel Placement Guidelines
      • Compiling the Design in the MegaWizard Plug-In Manager Design Flow
    • Compiling the Design in the Qsys Design Flow
    • Modifying the Example Design
  • 3. Getting Started with the Avalon-MM Arria Hard IP for PCI Express
    • Running Qsys
    • Customizing the Arria V Hard IP for PCI Express IP Core
    • Adding the Remaining Components to the Qsys System
    • Completing the Connections in Qsys
    • Specifying Clocks and Interrupts
    • Specifying Exported Interfaces
    • Specifying Address Assignments
    • Simulating the Example Design
    • Simulating the Single DWord Design
    • Understanding Channel Placement Guidelines
    • Adding Synopsis Design Constraints
    • Creating a Quartus II Project
    • Compiling the Design
    • Programming a Device
  • 4. Parameter Settings for the Arria V Hard IP for PCI Express
    • System Settings
    • Port Functions
      • Parameters Shared Across All Port Functions
        • Device
        • Error Reporting
        • Link
        • Slot
        • Power Management
      • Parameters Defined Separately for All Port Functions
        • Base Address Registers for Function <n>
        • Base and Limit Registers for Root Port Func <n>
        • Device ID Registers for Function <n>
        • PCI Express/PCI Capabilities for Func <n>
  • 5. Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express
    • System Settings
    • Base Address Registers
    • Device Identification Registers
    • PCI Express/PCI Capabilities
      • Device
      • Error Reporting
      • Link
      • Power Management
    • Avalon Memory-Mapped System Settings
    • Avalon to PCIe Address Translation Settings
  • 6. IP Core Architecture
    • Key Interfaces
      • Avalon-ST Interface
        • RX Datapath
        • TX Datapath
      • Clocks and Reset
      • Local Management Interface (LMI Interface)
      • Transceiver Reconfiguration
      • Interrupts
      • PIPE
    • Protocol Layers
      • Transaction Layer
        • Configuration Space
      • Data Link Layer
      • Physical Layer
    • Multi-Function Support
    • PCI Express Avalon-MM Bridge
    • Avalon-MM Bridge TLPs
      • Avalon-MM-to-PCI Express Write Requests
      • Avalon-MM-to-PCI Express Upstream Read Requests
      • PCI Express-to-Avalon-MM Read Completions
      • PCI Express-to-Avalon-MM Downstream Write Requests
      • PCI Express-to-Avalon-MM Downstream Read Requests
      • Avalon-MM-to-PCI Express Read Completions
      • PCI Express-to-Avalon-MM Address Translation for Endpoints
      • Minimizing BAR Sizes and the PCIe Address Space
      • Avalon-MM-to-PCI Express Address Translation Algorithm
    • Single DWord Completer Endpoint
      • RX Block
      • Avalon-MM RX Master Block
      • TX Block
      • Interrupt Handler Block
  • 7. IP Core Interfaces
    • Arria V Hard IP for PCI Express
      • Avalon-ST Packets to PCI Express TLPs
      • Avalon-ST RX Interface
        • Data Alignment and Timing for the 64-Bit Avalon-ST RX Interface
        • Data Alignment and Timing for the 128-Bit Avalon-ST RX Interface
      • Avalon-ST TX Interface
        • Data Alignment and Timing for the 64-Bit Avalon-ST TX Interface
        • Data Alignment and Timing for the 128-Bit Avalon-ST TX Interface
        • Root Port Mode Configuration Requests
        • ECRC Forwarding
      • Clock Signals
      • Reset Signals
      • ECC Error Signals
      • Interrupts for Endpoints
      • Interrupts for Root Ports
      • Completion Side Band Signals
      • Transaction Layer Configuration Space Signals
        • Configuration Space Register Access Timing
        • Configuration Space Register Access
      • LMI Signals
        • LMI Read Operation
        • LMI Write Operation
      • Power Management Signals
    • Avalon-MM Hard IP for PCI Express
      • 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
      • RX Avalon-MM Master Signals
      • 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
    • Physical Layer Interface Signals
      • Transceiver Reconfiguration
      • Serial Interface Signals
      • PIPE Interface Signals
    • Test Signals
  • 8. Register Descriptions
    • Configuration Space Register Content
    • Altera-Defined Vendor Specific Extended Capability (VSEC)
    • PCI Express Avalon-MM Bridge Control Register Access Content
      • Avalon-MM to PCI Express Interrupt Registers
      • PCI Express Mailbox Registers
      • Avalon-MM-to-PCI Express Address Translation Table
      • Root Port TLP Data Registers
      • Programming Model for Avalon-MM Root Port
        • Sending a TLP
        • Receiving a Completion TLP
      • PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports
      • PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
      • Avalon-MM Mailbox Registers
    • Correspondence between Configuration Space Registers and the PCIe Spec 2.1
  • 9. Reset and Clocks
    • Reset
    • Clocks
      • pclk
      • coreclkout_hip
      • pld_clk
      • Transceiver Clock Signals
  • 10. Transaction Layer Protocol (TLP) Details
    • Supported Message Types
    • Transaction Layer Routing Rules
    • Receive Buffer Reordering
  • 11. Interrupts
    • Interrupts for Endpoints Using the Avalon-ST Application Interface
      • MSI Interrupts
      • MSI-X
      • Legacy Interrupts
    • Interrupts for Root Ports Using the Avalon-ST Interface to the Application Layer
    • Interrupts for Endpoints Using the Avalon-MM Interface to the Application Layer
      • Enabling MSI or Legacy Interrupts
      • Generation of Avalon-MM Interrupts
    • Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
  • 12. Optional Features
    • Configuration via Protocol (CvP)
    • ECRC
      • ECRC on the RX Path
      • ECRC on the TX Path
    • Lane Initialization and Reversal
  • 13. Flow Control
    • Throughput of Posted Writes
    • Throughput of Non-Posted Reads
  • 14. Error Handling
    • Physical Layer Errors
    • Data Link Layer Errors
    • Transaction Layer Errors
    • Error Reporting and Data Poisoning
    • Uncorrectable and Correctable Error Status Bits
  • 15. Transceiver PHY IP Reconfiguration
  • 16. SDC Timing Constraints
    • SDC Constraints for the Hard IP for PCIe
    • SDC Constraints for the Example Design
  • 17. Testbench and Design Example
    • Endpoint Testbench
    • Root Port Testbench
    • Chaining DMA Design Examples
      • Design Example BAR/Address Map
      • Chaining DMA Control and Status Registers
      • Chaining DMA Descriptor Tables
    • Test Driver Module
      • DMA Write Cycles
      • DMA Read Cycles
    • Root Port Design Example
    • Root Port BFM
      • BFM Memory Map
      • Configuration Space Bus and Device Numbering
      • Configuration of Root Port and Endpoint
      • Issuing Read and Write Transactions to the Application Layer
    • BFM Procedures and Functions
      • BFM Read and Write Procedures
        • ebfm_barwr Procedure
        • ebfm_barwr_imm Procedure
        • ebfm_barrd_wait Procedure
        • ebfm_barrd_nowt Procedure
        • ebfm_cfgwr_imm_wait Procedure
        • ebfm_cfgwr_imm_nowt Procedure
        • ebfm_cfgrd_wait Procedure
        • ebfm_cfgrd_nowt Procedure
      • BFM Configuration Procedures
        • ebfm_cfg_rp_ep Procedure
        • ebfm_cfg_decode_bar Procedure
      • BFM Shared Memory Access Procedures
        • Shared Memory Constants
        • shmem_write
        • shmem_read Function
        • shmem_display Verilog HDL Function
        • shmem_fill Procedure
        • shmem_chk_ok Function
      • BFM Log and Message Procedures
        • ebfm_display Verilog HDL Function
        • ebfm_log_stop_sim Verilog HDL Function
        • ebfm_log_set_suppressed_msg_mask Verilog HDL Function
        • ebfm_log_set_stop_on_msg_mask Verilog HDL Function
        • ebfm_log_open Verilog HDL Function
        • ebfm_log_close Verilog HDL Function
      • Verilog HDL Formatting Functions
        • himage1
        • himage2
        • himage4
        • himage8
        • himage16
        • dimage1
        • dimage2
        • dimage3
        • dimage4
        • dimage5
        • dimage6
        • dimage7
      • Procedures and Functions Specific to the Chaining DMA Design Example
        • chained_dma_test Procedure
        • dma_rd_test Procedure
        • dma_wr_test Procedure
        • dma_set_rd_desc_data Procedure
        • dma_set_wr_desc_data Procedure
        • dma_set_header Procedure
        • rc_mempoll Procedure
        • msi_poll Procedure
        • dma_set_msi Procedure
        • find_mem_bar Procedure
        • dma_set_rclast Procedure
        • ebfm_display_verb Procedure
  • 18. Debugging
    • Hardware Bring-Up Issues
    • Link Training
    • Link Hangs in L0 Due To Deassertion of tx_st_ready
    • Recommended Reset Sequence to Avoid Link Training Issues
    • Setting Up Simulation
      • Changing Between Serial and PIPE Simulation
      • Use the PIPE Interface for Gen1 and Gen2 Variants
      • Reduce Counter Values for Serial Simulations
      • Disable the Scrambler for Gen1 and Gen2 Simulations
      • Change between the Hard and Soft Reset Controller
    • ).Use Third-Party PCIe Analyzer
    • BIOS Enumeration Issues
  • A. Transaction Layer Packet (TLP) Header Formats
    • TLP Packet Format without Data Payload
    • TLP Packet Format with Data Payload
  • Additional Information
    • Revision History
    • How to Contact Altera
    • Typographic Conventions