Altera Embedded Peripherals IP - Manual (Page 107)

SPI Core
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Core Overview
SPI is an industry-standard serial protocol commonly used in embedded systems to connect
microprocessors to a variety of off-chip sensor, conversion, memory, and control devices. The SPI core
with Avalon ® interface implements the SPI protocol and provides an Avalon Memory-Mapped (Avalon-
MM) interface on the back end.
The SPI core can implement either the master or slave protocol. When configured as a master, the SPI
core can control up to 32 independent SPI slaves. The width of the receive and transmit registers are
configurable between 1 and 32 bits. Longer transfer lengths can be supported with software routines. The
SPI core provides an interrupt output that can flag an interrupt whenever a transfer completes.
Functional Description
The SPI core communicates using two data lines, a control line, and a synchronization clock:
• Master Out Slave In (
mosi
)—Output data from the master to the inputs of the slaves
• Master In Slave Out (
miso
)—Output data from a slave to the input of the master
• Serial Clock (
sclk
)—Clock driven by the master to slaves, used to synchronize the data bits
• Slave Select (
ss_n
)— Select signal (active low) driven by the master to individual slaves, used to select
the target slave
The SPI core has the following user-visible features:
• A memory-mapped register space comprised of five registers:
rxdata
,
txdata
,
status
,
control
, and
slaveselect
• Four SPI interface ports:
sclk
,
ss_n
,
mosi
, and
miso
The registers provide an interface to the SPI core and are visible via the Avalon-MM slave port. The
sclk
,
ss_n
,
mosi
, and
miso
ports provide the hardware interface to other SPI devices. The behavior of
sclk
,
ss_n
,
mosi
, and
miso
depends on whether the SPI core is configured as a master or slave.
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