Introduction, Tool support, Obsolescence – Altera Embedded Peripherals IP User Manual
Page 14: Introduction -1, Tool support -1, Obsolescence -1
Introduction
1
2014.24.07
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This user guide describes the IP cores provided by Altera that are included in the Quartus
®
II design
software.
The IP cores are optimized for Altera
®
devices and can be easily implemented to reduce design and test
time. You can use the IP parameter editor from Qsys to add the IP cores to your system, configure the
cores, and specify their connectivity.
Altera's Qsys system integration tool is available in the Quartus II software subcription edition version
14.0.
Before using Qsys, review the (Quartus II software Version 14.0 Release Notes) for known issues and
limitations. To submit general feedback or technical support, click Feedback on the Quartus II software
Help menu and also on all Altera technical documentation.
Tool Support
Qsys is a system-level integration tool which is included as part of the Quartus II software. Qsys leverages
the easy-to-use interface of SOPC Builder and provides backward compatibility for easy migration of
existing embedded systems.You can implement a design using the IP cores from the Qsys component
library.
All the IP cores described in this user guide are supported by Qsys except for the following cores which
are only supported by SOPC Builder.
• Common Flash Interface Controller Core
• SDRAM Controller Core (pin-sharing mode)
• System ID Core
Obsolescence
The following IP cores are scheduled for product obsolescence and discontinued support:
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