Altera Embedded Peripherals IP - Manual (Page 70)

UART Core
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2014.24.07
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Core Overview
The UART core with Avalon ® interface implements a method to communicate serial character streams
between an embedded system on an Altera FPGA and an external device. The core implements the
RS-232 protocol timing, and provides adjustable baud rate, parity, stop, and data bits, and optional
RTS/CTS flow control signals. The feature set is configurable, allowing designers to implement just the
necessary functionality for a given system.
The core provides an Avalon Memory-Mapped (Avalon-MM) slave interface that allows Avalon-MM
master peripherals (such as a Nios II processor) to communicate with the core simply by reading and
writing control and data registers.
Functional Description
Figure 8-1: Block Diagram of the UART Core in a Typical System
Altera FPGA
UART Core
baud rate divisor
shift register
RXD
RTS
CTS
TXD L
e
v
el
Shifter
RS - 232 Connector
Avalon-MM
signals
connected
to on-chip
logic
data
IRQ
dataavailable
readyfordata
endofpacket
address
clock
rxdata
status
control
txdata
endofpacket
shift register
divisor
The core has two user-visible parts:
• The register file, which is accessed via the Avalon-MM slave port
• The RS-232 signals,
RXD
,
TXD
,
CTS
, and
RTS
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