Altera Embedded Peripherals IP - Manual (Page 289)

Descrip‐
tion:
Specifies the linker section that each VIC's generated vector table
and each interrupt funnel link to. The memory device that the
specified linker section is mapped to must be connected to both
the Nios II instruction and data masters in your SOPC Builder
system.
Use this setting to link performance-critical code into faster
memory. For example, if your system's code is in DRAM and
you have an on-chip or tightly-coupled memory interface for
interrupt handling code, assigning the VIC driver linker section
to a section in that memory improves interrupt response time.
For more information about linker sections and the Nios II BSP
Editor, refer to the Getting Started with the Graphical User
Interface chapter of the Nios II Software Developer’s Handbook.
Occurs: Once per VIC
altera_vic_driver.<name>.vec_size
Identifier: <name>_VEC_SIZE
Type:
DecimalNumber
Default
value:
16
Destina‐
tion file:
system.h
Descrip‐
tion:
Specifies the number of bytes in each vector table entry. Legal
values are 16, 32, 64, 128, 256, and 512.
The generated VIC vector tables in the BSP require a minimum
of 16 bytes per entry.
If you intend to write your own vector table or locate your ISR at
the vector address, you can use a larger size.
The vector table's total size is equal to the number of interrupt
ports on the VIC instance multiplied by the vector table entry
size specified in this setting.
Occurs: Per instance; <name> refers to the component name you assign
in SOPC Builder.
altera_vic_driver.<name>.irq<n>_rrs
Identifier: ALTERA_VIC_DRIVER_<name>_IRQ<n>_RRS
Type:
DecimalNumber
Default
value:
Refer to the Default Settings for RRS and RIL section.
28-20 altera_vic_driver.<name>.vec_size
UG-01085
2014.24.07
Altera Corporation Vectored Interrupt Controller Core
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