Altera Embedded Peripherals IP - Manual (Page 253)

this timer. The driver is interrupt-driven, and therefore must have its interrupt signal connected in the
system hardware.
The Nios II integrated development environment (IDE) allows you to specify system library properties
that determine which timer device will be used as the system clock timer.
Timestamp Driver
The interval timer core may be used as a timestamp device if it meets the following conditions:
• The timer has a writeable
period
register, as configured in Qsys.
• The timer is not selected as the system clock.
The Nios II IDE allows you to specify system library properties that determine which timer device will
be used as the timestamp timer.
If the timer hardware is not configured with writeable
period
registers, calls to the
alt_timestamp_start()
API function will not reset the timestamp counter. All other HAL API calls
will perform as expected.
For more information about using the system clock and timestamp features that use these drivers, refer
to the Nios II Software Developer’s Handbook. The Nios II Embedded Design Suite (EDS) also
provides several example designs that use the interval timer core.
Limitations
The HAL driver for the interval timer core does not support the watchdog reset feature of the core.
Software Files
The interval timer core is accompanied by the following software files. These files define the low-level
interface to the hardware, and provide the HAL drivers. Application developers should not modify these
files.
• altera_avalon_timer_regs.h—This file defines the core's register map, providing symbolic constants
to access the low-level hardware.
• altera_avalon_timer.h , altera_avalon_timer_sc.c, altera_avalon_timer_ts.c,
altera_avalon_timer_vars.c—These files implement the timer device drivers for the HAL system
library.
Register Map
You do not need to access the interval timer core directly via its registers if using the standard features
provided in the HAL system library for the Nios II processor. In general, the register map is only useful to
programmers writing a device driver.
The Altera-provided HAL device driver accesses the device registers directly. If you are writing a device
driver, and the HAL driver is active for the same device, your driver will conflict and fail to operate
correctly.
The table below shows the register map for the 32-bit timer. The interval timer core uses native address
alignment. For example, to access the
control
register value, use offset 0x4.
UG-01085
2014.24.07
Software Files 25-5
Interval Timer Core Altera Corporation
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