Altera Embedded Peripherals IP - Manual (Page 38)

Signal Width Direction Description
sdram_cke 1 Output SDRAM Clock Enable. The
SDRAM controller does not
support clock-disable modes.
The SDRAM controller
permanently asserts the
tcm_
sdr_cke_out
signal on the
SDRAM.
Note: The SDRAM controller does not have any configurable control status registers (CSR).
Reset and Clock Requirements
The main reset input signal to the SDRAM is treated as an asynchronous reset input from the SDRAM
core perspective. A reset synchronizer circuit, as typically implemented for each reset domain in a
complete SOC/ASIC system is not implemented within the SDRAM core. Instead, this reset synchronizer
circuit should be implemented externally to the SDRAM, in a higher hierarchy within the complete
system design, so that the “asynchronous assertion, synchronous de-assertion” rule is fulfilled.
The SDRAM core accepts an input clock at its
clk
input with maximum frequency of 100-MHz. The
other requirements for the clock, such as its minimum frequency should be similar to the requirement of
the external SDRAM which the SDRAM is interfaced to.
Architecture
The SDRAM Controller connects to one or more SDRAM chips, and handles all SDRAM protocol
requirements. Internal to the device, the core presents an Avalon-MM slave ports that appears as a linear
memory (flat address space) to Avalon-MM master device.
The core can access SDRAM subsystems with:
• Various data widths (8-, 16-, 32- or 64-bits)
• Various memory sizes
• Multiple chip selects
The Avalon-MM interface is latency-aware, allowing read transfers to be pipelined. The core can
optionally share its address and data buses with other off-chip Avalon-MM tri-state devices.
Note: Limitations: for now the arbitration control of this mode should be handled by the host/master in
the system to avoid a device monopolizing the shared buses.
Control logic within the SDRAM core responsible for the main functionality listed below, among others:
• Refresh operation
• Open_row management
• Delay and command management
Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data
written to the DRAM must be presented in the same cycle as the write command, but reads produce
output 2 or 3 cycles after the read command. The SDRAM controller must ensure that the data bus is
never required for a read and a write at the same time.
3-8 Reset and Clock Requirements
UG-01085
2014.24.07
Altera Corporation Tri-State SDRAM
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