Altera Embedded Peripherals IP - Manual (Page 151)

MDIO Core
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The Altera Management Data Input/Output (MDIO) IP core is a two-wire standard management
interface that implements a standardized method to access the external Ethernet PHY device management
registers for configuration and management purposes. The MDIO IP core is IEEE 802.3 standard
compliant.
To access each PHY device, the PHY register address must be written to the register space followed by the
transaction data. The PHY register addresses are mapped in the MDIO core’s register space and can be
accessed by the host processor via the Avalon ® Memory-Mapped (Avalon-MM) interface. This IP core
can also be used with the Altera 10-Gbps Ethernet MAC to realize a fully manageable system.
Functional Description
The core provides an Avalon Memory-Mapped (Avalon-MM) slave interface that allows Avalon-MM
master peripherals (such as a CPU) to communicate with the core and access the external PHY by reading
and writing the control and data registers. The system interconnect fabric connects the Avalon-MM
master and slave interface while a buffer connects the MDIO interface signals to the external PHY.
For more information about system interconnect fabric for Avalon-MM interfaces, refer to the
System
Interconnect Fabric for Memory-Mapped Interfaces .
Figure 15-1: MDIO Core Block Diagram
csr_address
mdio_in
MDIO Core mdio_out
clk
Avalon-MM
Slave
Interface
csr_waitrequest
MDIO
Ports
External PHY
mdc
mdio
csr_read
csr_write
csr_writedata
csr_readdata
reset
mdio_oen
MDIO Buffer
Connection
Altera FPGA
32
32
6
System
Inter-
connect
Fabric
User
Logic
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