Altera Embedded Peripherals IP - Manual (Page 73)

The baud rate value is used to calculate an appropriate clock divisor value to implement the desired baud
rate. Baud rate and divisor values are related as shown in the follow two equations:
Divisor Formula:
divisor int
clock frequency
baud rate
---------- ----------------- ------------ -- 0.5 +
(
=
)
Baud rate Formula:
baud rate
clock frequency
divisor 1 +
--------------- ---------------- -------- -- =
Baud Rate Can Be Changed By Software Setting
When this setting is on, the hardware includes a 16-bit
divisor
register at address offset 4. The
divisor
register is writable, so the baud rate can be changed by writing a new value to this register.
When this setting is off, the UART hardware does not include a
divisor
register. The UART hardware
implements a constant baud divisor, and the value cannot be changed after system generation. In this
case, writing to address offset 4 has no effect, and reading from address offset 4 produces an undefined
result.
Data Bits, Stop Bits, Parity
The UART core's parity, data bits and stop bits are configurable. These settings are fixed at system
generation time; they cannot be altered via the register file.
Table 8-1: Data Bits Settings
Setting Legal Values Description
Data
Bits
7, 8, 9 This setting determines the widths of the
txdata
,
rxdata
, and
endofpacket
registers.
Stop
Bits
1, 2 This setting determines whether the core transmits 1 or 2 stop bits with
every character. The core always terminates a receive transaction at the
first stop bit, and ignores all subsequent stop bits, regardless of this setting.
8-4 Baud Rate Can Be Changed By Software Setting
UG-01085
2014.24.07
Altera Corporation UART Core
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