Altera Embedded Peripherals IP - Manual (Page 244)

Parameter Name Description
Vertical Sync Pulse
Lines
The width of the v-sync pulse in number of lines.
Vertical Front Porch
Lines
The number of blanking lines that follow the active lines. During this
period, there is no data flow from the Avalon-ST sink port to the LCD
output data port.
Number of Columns The number of active pixels in each line.
Horizontal Blank
Pixels
The number of blanking pixels that precede the active pixels. During this
period, there is no data flow from the Avalon-ST sink port to the LCD
output data port.
Total Horizontal
Scan Pixels
The total number of pixels in one line. The value is the sum of the
following parameters: Number of Columns, Horizontal Blank Pixel, and
Horizontal Front Porch Pixels.
Beats Per Pixel The number of beats required to transfer one pixel. Valid values are 1 and
3. This parameter, when multiplied by Data Stream Bit Width must be
equal to the total number of bits in one pixel. This parameter affects the
operating clock frequency, as shown in the following equation:
Operating clock frequency = (Beats per pixel) * (Pixel_rate), where
Pixel_rate (in MHz) = ((Total Horizontal Scan Pixels) * (Total Vertical
Scan Lines) * (Display refresh rate in Hz))/1000000.
Vertical Blank Lines The number of blanking lines that proceed the active lines. During this
period, there is no data flow from the Avalon-ST sink port to the LCD
output data port.
Data Stream Bit
Width
The width of the inbound and outbound data.
Signals
Table 24-2: Video Sync Generator Core Signals
Signal Name Width (Bits) Direction Description
Global Signals
clk
1 Input System clock.
reset 1 Input System reset.
Avalon-ST Signals
data
Variable-
width
Input Incoming pixel data. The datawidth is determined by the
parameter Data Stream Bit Width.
ready
1 Output This signal is asserted when the video sync generator is
ready to receive the pixel data.
UG-01085
2014.24.07
Signals 24-3
Video Sync Generator and Pixel Converter Cores Altera Corporation
Send Feedback