Compact flash core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 41: Compact flash core -1, Core overview -1, Functional description -1, Figure 4-1: system with a compactflash core
Compact Flash Core
4
2014.24.07
UG-01085
Core Overview
The CompactFlash core allows you to connect systems built on Osys to CompactFlash storage cards in
true IDE mode by providing an Avalon
®
Memory-Mapped (Avalon-MM) interface to the registers on the
storage cards. The core supports PIO mode 0.
The CompactFlash core also provides an Avalon-MM slave interface which can be used by Avalon-MM
master peripherals such as a Nios
®
II processor to communicate with the CompactFlash core and manage
its operations.
Functional Description
Figure 4-1: System With a CompactFlash Core
Avalon-to-
CompactFlash
Avalon-MM
Master
(e.g. CPU)
System Interconnect
Fab
ric
Altera FPGA
CompactFlash
Device
e
di
al
S
M
M-
n
ol
a
v
A
r
o
P
e
v
t
ctl
al
S
M
M-
n
ol
a
v
A
r
o
P
e
v
t
data
address
cfctl
idectl
Registers
IRQ
data
address
IRQ
As shown in the block diagram, the CompactFlash core provides two Avalon-MM slave interfaces: the
ide
slave port for accessing the registers on the CompactFlash device and the
ctl
slave port for accessing the
core's internal registers. These registers can be used by Avalon-MM master peripherals such as a Nios II
processor to control the operations of the CompactFlash core and to transfer data to and from the
CompactFlash device.
You can set the CompactFlash core to generate two active-high interrupt requests (IRQs): one signals the
insertion and removal of a CompactFlash device and the other passes interrupt signals from the Compact‐
Flash device.
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