Altera Embedded Peripherals IP - Manual (Page 325)

Signal Width Direction Description
write
1 Input Avalon-MM write
control
writedata
32 Input Avalon-MM write data
bus
readdata
32 Output Avalon-MM read data
bus
Table 33-7: Serial Interface
Signal Width Direction Description
smb_clk_oe
1 Output Outgoing SMBus clock.
Output enable for open
drain buffer that drives
SMBCLK
pin. When 1,
SMBCLK
line is expected
to be pulled low. When 0,
open drain buffer is tri-
stated and
SMBCLK
line is
externally pulled high.
smb_data_oe
1 Output Outgoing SMBus data.
Output enable for open
drain buffer that drives
SMBDAT
pin. When 1,
SMBDAT
line is expected
to be pulled low. When 0,
open drain buffer is tri-
stated and
SMBDAT
line is
externally pulled high.
smb_clk_in
1 Input Incoming SMBus clock,
from the input path of
the
SMBCLK
open drain
buffer.
smb_data_in
1 Input Incoming SMBus data,
from the input path of
the
SMBDAT
open drain
buffer.
Table 33-8: Interrupt
Signal Width Direction Description
smb_intr
1 Output Interrupt output to host
processor, active high.
33-6 Altera SMBus Core Interface
UG-01085
2014.24.07
Altera Corporation Altera MSI to GIC Generator
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