Altera Embedded Peripherals IP - Manual (Page 177)

Avalon-MM Interfaces
The core can have up to three Avalon-MM interfaces:
• Avalon-MM control interface—Allows master peripherals to set and access almost-full and almost-
empty thresholds. The same set of thresholds is used by all channels. See Control Interface Register
Map figure for the description of the threshold registers.
• Avalon-MM fill-level interface—Allows master peripherals to retrieve the fill level of the FIFO buffer
for a given channel. The fill level represents the amount of data in the FIFO buffer at any given time.
The read latency on this interface is one. See the Fill-level Interface Register Map table for the
description of the fill-level registers.
• Avalon-MM request interface—Allows master peripherals to request data for a given channel. This
interface is implemented only when the Use Request parameter is turned on. The
request_address
signal contains the channel number. Only one word of data is returned for each request.
For more information about Avalon interfaces, refer to the
Avalon Interface Specifications .
Operation
The Avalon-ST Multi-Channel Shared FIFO core allocates dedicated memory segments within the core
for each channel, and is implemented such that the memory segments occupy a single memory block. The
parameter FIFO depth determines the depth of each memory segment.
The core receives data on its
in
interface (Avalon-ST sink) and stores the data in the allocated memory
segments. If a packet contains any error (
in_error
signal is asserted), the core drops the packet.
When the core receives a request on its
request
interface (Avalon-MM slave), it forwards the requested
data to its
out
interface (Avalon-ST source) only when it has received a full packet on its
in
interface. If
the core has not received a full packet or has no data for the requested channel, it deasserts the
valid
signal on its
out
interface to indicate that data is not available for the channel. The output latency is three
and only one word of data can be requested at a time.
When the Avalon-MM request interface is not in use, the
request_write
signal is kept asserted and the
request_address
signal is set to 0. Hence, if you configure the core to support more than one channel,
you must also ensure that the Use request parameter is turned on. Otherwise, only channel 0 is accessible.
You can configure almost-full thresholds to manage FIFO overflow. The current threshold status for each
channel is available from the core's Avalon-ST status interfaces in a round-robin fashion. For example, if
the threshold status for channel 0 is available on the interface in clock cycle n, the threshold status for
channel 1 is available in clock cycle n+1 and so forth.
Parameters
Table 17-5: Configurable Parameters
Parameter Legal Values Description
Number of channels 1, 2, 4, 8, and
16
The total number of channels supported on the Avalon-
ST data interfaces.
Symbols per beat 1–32 The number of symbols transferred in a beat on the
Avalon-ST data interfaces
Bits per symbol 1–32 The symbol width in bits on the Avalon-ST data
interfaces.
17-4 Operation
UG-01085
2014.24.07
Altera Corporation Avalon-ST Multi-Channel Shared Memory FIFO Core
Send Feedback