Spi slave/jtag to avalon master bridge cores, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 182: Spi slave/jtag to avalon master bridge cores -1, Core overview -1, Functional description -1, The spi slave to avalon
SPI Slave/JTAG to Avalon Master Bridge Cores
18
2014.24.07
UG-01085
Core Overview
The SPI Slave to Avalon
®
Master Bridge and the JTAG to Avalon Master Bridge cores provide a
connection between host systems and Qsys systems via the respective physical interfaces. Host systems
can initiate Avalon Memory-Mapped (Avalon-MM) transactions by sending encoded streams of bytes via
the cores’ physical interfaces. The cores support reads and writes, but not burst transactions.
Functional Description
Figure 18-1: System with a SPI Slave to Avalon Master Bridge Core
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Rest of the
System
SPI
Master
(Example:
Po wer PC
Processor)
Altera FPGA
SPI to Transaction Bridge
src
k
ni
s
Avalon-ST
Bytes to
Packets
Converter
src
k
ni
s
Avalon-ST
Packets to
Transactions
Converter
A
v
alon-MM Mas
te
r
src
Avalon-ST
Source
sink
Avalon-ST
Sink
src
k
ni
s
Avalon-ST
Packets to
Bytes
Converter
Avalon-ST
SPI Core
SPI
src
k
ni
s
SPI
Clock
Clock
System
Clock
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