Altera Embedded Peripherals IP - Manual (Page 95)

data from the shift register is written onto the Receive Buffer. The existing data in the Receive Buffer is
overwritten. This is consistent with published PC16550D UART behavior.
Transmit Overrun Behavior
When the host CPU forcefully triggers a transmit Overrun, the Soft-UART handles it differently
depending on FIFO mode. With FIFO enabled, the newly written data is lost. With FIFO disabled, the
newly written data will overwrite the existing data in the Transmit Holding Register.
Underrun
No mechanisms exist to detect or prevent underrun.
On transmit path, an interrupts, when enabled, can be generated when the transmit holding register is
empty or when the transmit FIFO is below a programmed level.
On receive path, the software driver is expected to read from the UART receive buffer (FIFO-less) or the
(Rx FIFO) based on interrupts, when enabled, or status registers indicating presence of receive data (Data
Ready bit, LSR[0]). If reads to Receive Buffer Register is triggered with the data ready register being zero,
the previously read data is returned.
Hardware Auto Flow-Control
Hardware based auto flow-control uses 2 signals (
cts_n
&
rts_n
) from the Modem Control/Status group.
With Hardware auto flow-control disabled, these signals will directly drive the Modem Status register
(
cts_n
) or be driven by the Modem Control register (
rts_n
).
With auto flow-control enabled, these signals perform flow-control duty with another UART at the other
end.
The
cts_n
input is, when active (low state), will allow the Tx FIFO to send data to the transmit buffer.
When
cts_n
is inactive (high state), the Tx FIFO stops sending data to the transmit buffer.
cts_n
is
expected to be connected to the
rts_n
output of the other UART.
The
rts_n
output will go active (low state), when the Rx FIFO is empty, signaling to the opposite UART
that it is ready for data. The
rts_n
output goes inactive (high state) when the Rx FIFO level is reached,
signaling to the opposite UART that the FIFO is about to go full and it should stop transmitting.
Due to the delays within the UART logic, one additional character may be transmitted after
cts_n
is
sampled active low. For the same reason, the Rx FIFO will accommodate up to 1 additional character after
asserting
rts_n
(this is allowed because Rx FIFO trigger level is at worst, two entries from being truly
full). Both are observed to prevent overflow/underflow between UARTs.
UG-01085
2014.24.07
Transmit Overrun Behavior 9-9
16550 UART Altera Corporation
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