Avalon-st serial peripheral interface core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 131: Interfaces, Avalon-st serial peripheral interface core -1, Core overview -1, Functional description -1, Interfaces -1, The avalon, Figure 13-1: system with an avalon-st spi core
Avalon-ST Serial Peripheral Interface Core
13
2014.24.07
UG-01085
Core Overview
The Avalon
®
Streaming (Avalon-ST) Serial Peripheral Interface (SPI) core is an SPI slave that allows data
transfers between Qsys systems and off-chip SPI devices via Avalon-ST interfaces. Data is serially
transferred on the SPI, and sent to and received from the Avalon-ST interface in bytes.
The SPI Slave to Avalon Master Bridge is an example of how this core is used.
For more information on the bridge, refer to
Avalon-ST Serial Peripheral Interface Core
.
Functional Description
Figure 13-1: System with an Avalon-ST SPI Core
Avalon-ST
Source
Avalon-ST
Sink
Avalon-ST
Serial
Peripheral
Interface
Core
SPI
a
F t
c
e
n
n
o
cr
et
nI
m
et
s
y
S
b
cir
Rest of the
System
data_out
data_in
SPI
Master
mosi
miso
sclk
nSS
Altera FPGA
SPI
Clock
System
Clock
Interfaces
The serial peripheral interface is full-duplex and does not support backpressure. It supports SPI clock
phase bit, CPHA = 1, and SPI clock polarity bit, CPOL = 0.
Table 13-1: Properties of Avalon-ST Interfaces
Feature
Property
Backpressure
Not supported.
Data Width
Data width = 8 bits; Bits per symbol = 8.
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