Altera Embedded Peripherals IP - Manual (Page 136)

PCI
Device
Mode
PCI Target PCI Master ALUTs (2) Logic
Register
M9K Memory
Blocks
I/O Pins
Max (1) Enabled Enabled 1,347 876 5 50
Table 14-1 :
1. Min = One BAR with minimum settings for each parameter.
Max = Three BARs with maximum settings for each parameter.
2. The logic element (LE) count for the Stratix III family is based on the number of adaptive
look-up tables (ALUTs) used for the design as reported by the Quartus II software.
Below the table lists the resource utilization and performance data for a Cyclone III device
(EP3C40F780C6).
Table 14-2: Memory Utilization and Performance Data for the Cyclone III Family
PCI
Device
Mode
PCI Target PCI Master Logic
Elements
Logic
Register
M4K Memory
Blocks
I/O Pins
Min (1) Enabled N/A 1,057 511 2 48
Max (1) Enabled Enabled 2,027 878 5 50
Table 14-2 :
1. Min = One BAR with minimum settings for each parameter.
Max = Three BARs with maximum settings for each parameter.
Functional Description
The following sections provide a functional description of the PCI Lite Core.
PCI-Avalon Bridge Blocks
The PCI-Avalon bridge's blocks manage the connectivity for the following PCI operational modes:
• PCI Target-Only Peripheral
• PCI Master/Target Peripheral
• PCI Host-Bridge Device
Depending on the operational mode, the PCI-Avalon bridge uses some or all of the predefined Avalon-
MM ports. The Generic PCI Avalon Bride Block Diagram shows a generic PCI-Avalon bridge block
diagram, which includes the following blocks:
• Five predefined Avalon-MM ports
• Control registers
• PCI master controller (when applicable)
• PCI target controller
14-2 Functional Description
UG-01085
2014.24.07
Altera Corporation PCI Lite Core
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