Tri-state sdram, Feature description, Tri-state sdram -1 – Altera Embedded Peripherals IP User Manual
Page 31: Feature description -1
Tri-State SDRAM
3
2014.24.07
UG-01085
The SDRAM controller core with Avalon
®
interface provides an Avalon Memory-Mapped (Avalon-MM)
interface to off-chip SDRAM. The SDRAM controller allows designers to create custom systems in an
Altera device that connect easily to SDRAM chips. The SDRAM controller supports standard SDRAM
defined by the PC100 specification.
SDRAM is commonly used in cost-sensitive applications requiring large amounts of volatile memory.
While SDRAM is relatively inexpensive, control logic is required to perform refresh operations, open-row
management, and other delays and command sequences. The SDRAM controller connects to one or more
SDRAM chips, and handles all SDRAM protocol requirements. The SDRAM controller core presents an
Avalon-MM slave port that appears as linear memory (flat address space) to Avalon-MM master
peripherals.
The Avalon-MM interface is latency-aware, allowing read transfers to be pipelined. The core can
optionally share its address and data buses with other off-chip Avalon-MM tri-state devices. This feature
is valuable in systems that have limited I/O pins, yet must connect to multiple memory chips in addition
to SDRAM.
The Tri-State SDRAM has the same functionality as the SDRAM Controller Core with the addition of the
Tri-State feature.
Feature Description
The SDRAM controller core has the following features:
• Maximum frequency of 100-MHz
• Single clock domain design
• Sharing of
dq
/
dqm
/
addr I
/
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