Altera Embedded Peripherals IP - Manual (Page 54)

software, the EPCS serial flash controller core signals are routed automatically to the device pins for the
EPCS device.
You, however, have the option not to use the dedicated pins on the FPGA (active serial configuration
mode) by turning off the respective parameters in the MegaWizard interface. When this option is turned
off or when the target device is a Cyclone III or Cyclone IV device, you have the flexibility to connect the
output pins, which are exported to the top-level design, to any EPCS devices. Perform the following tasks
in the Quartus ® II software to make the necessary pin assignments:
• On the Dual-purpose pins page (Assignments > Devices > Device and Pin Options), ensure that the
following pins are assigned to the respective values:
•
Data[0]
= Use as regular I/O
•
Data[1]
= Use as regularr I/O
•
DCLK
= Use as regular I/O
•
FLASH_nCE/nCS0
= Use as regular I/O
• Using the Pin Planner (Assignments > Pins), ensure that the following pins are assigned to the
respective configuration functions on the device:
•
data0_to_the_epcs_controller
=
DATA0
•
sdo_from the_epcs_controller
=
DATA1,ASDO
•
dclk_from_epcs_controller
=
DCLK
•
sce_from_the_epcs_controller
=
FLASH_nCE
Pin-Out Files for Altera Device
For more information about the configuration pins in Altera devices, refer to the Pin-Out Files for Altera
Device page.
Avalon-MM Slave Interface and Registers
The EPCS serial flash controller core has a single Avalon-MM slave interface that provides access to both
boot-loader code and registers that control the core. As shown in below, the first segment is dedicated to
the boot-loader code, and the next seven words are control and data registers. A Nios II CPU can read the
instruction words, starting from the core's base address as flat memory space, which enables the CPU to
reset the core's address space.
The EPCS serial flash controller core includes an interrupt signal that can be used to interrupt the CPU
when a transfer has completed.
Table 6-1: EPCS Serial Flash Controller Core Register Map
Offset
(32-bit Word Address)
Register Name R/W
Bit Description
31:0
0x00 .. 0xFF Boot ROM Memory
R Boot Loader
Code
UG-01085
2014.24.07
Avalon-MM Slave Interface and Registers 6-3
EPCS Serial Flash Controller Core Altera Corporation
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