Altera Embedded Peripherals IP - Manual (Page 330)

Figure 34-1: Usage model of Interrupt Latency Calculator
Processor
Interrupt Latency
Calculator
Peripheral
Data
Master
IRQ
Receiver
CSR
Slave
IRQ
Receiver
IRQ
Sender
Feature Description
The Altera Interrupt Latency Counter is made up of three sub functional blocks. The top level interface is
Avalon-MM protocol compliant. The interrupt detector block will be activated by the rising edge of the
interrupt signal or pulse, determined by a parameter during component generation. The Interrupt
detector block determines when to start or stop the 32-bit internal counter, which is reset to zero every
time it begins operation without affecting previous stored latency data register value. The Latency data
register is updated after the counter is stopped.
Each Interrupt Latency Counter can be configured to host up to 32 identical counters to monitor separate
IRQ channels. Each counter only observes one interrupt input. The interrupt could be level sensitive or
pulse (edge) sensitive. In the case where more interrupt lines need to be monitored, multiple Interrupt
Latency Counters could be instantiated in Qsys.
Interrupt Latency Calculator only keeps track of the latest interrupt latency value. If multiple interrupts
are happening in series, only the last interrupt latency will be maintained. On the other hand, every start
of interrupt edge refreshes the internal counter from zero.
Avalon-MM Compliant CSR Registers
Each ILC has rows of status registers each being 32 bits in length. The last four rows of CSR registers
corresponding to address 0x20 to 0x23 are fixed regardless of the number of IRQ port count configured
through the Qsys GUI Stop Address 0x0 to 0x1F. The Qsys GUI Stop Address is reserved to store the
latency value which depends on the number of IRQ port configured. For example, if you configure the
34-2 Feature Description
UG-01085
2014.24.07
Altera Corporation Altera Interrupt Latency Counter
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