Altera Embedded Peripherals IP - Manual (Page 72)

A master peripheral can monitor the receiver's status by reading the
status
register's read-ready (
RRDY
),
receiver-overrun error (
ROE
), break detect (
BRK
), parity error (
PE
), and framing error (
FE
) bits. The
receiver logic automatically detects the correct number of start, stop, and parity bits in the serial RXD
stream as required by the RS-232 specification. The receiver logic checks for four exceptional conditions,
frame error, parity error, receive overrun error, and break, in the received data and sets corresponding
status
register bits.
Baud Rate Generation
The UART core's internal baud clock is derived from the Avalon-MM clock input. The internal baud
clock is generated by a clock divider. The divisor value can come from one of the following sources:
• A constant value specified at system generation time
• The 16-bit value stored in the
divisor
register
The
divisor
register is an optional hardware feature. If it is disabled at system generation time, the
divisor value is fixed and the baud rate cannot be altered.
Instantiating the Core
Instantiating the UART in hardware creates at least two I/O ports for each UART core: An
RXD
input, and
a
TXD
output. Optionally, the hardware may include flow control signals, the
CTS
input and
RTS
output.
The following sections describe the available options.
Configuration Settings
This section describes the configuration settings.
Baud Rate Options
The UART core can implement any of the standard baud rates for RS-232 connections. The baud rate can
be configured in one of two ways:
• Fixed rate—The baud rate is fixed at system generation time and cannot be changed via the Avalon-
MM slave port.
• Variable rate—The baud rate can vary, based on a clock divisor value held in the
divisor
register. A
master peripheral changes the baud rate by writing new values to the
divisor
register.
The baud rate is calculated based on the clock frequency provided by the Avalon-MM interface.
Changing the system clock frequency in hardware without regenerating the UART core hardware
results in incorrect signaling.
The baud rate is calculated based on the clock frequency provided by the Avalon-MM interface. Changing
the system clock frequency in hardware without regenerating the UART core hardware results in
incorrect signaling.
Baud Rate (bps) Setting
The Baud Rate setting determines the default baud rate after reset. The Baud Rate option offers standard
preset values.
UG-01085
2014.24.07
Baud Rate Generation 8-3
UART Core Altera Corporation
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