Vectored interrupt controller core, Core overview, Vectored interrupt controller core -1 – Altera Embedded Peripherals IP User Manual
Page 270: Core overview -1
Vectored Interrupt Controller Core
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Core Overview
The vectored interrupt controller (VIC) core serves the following main purposes:
• Provides an interface to the interrupts in your system
• Reduces interrupt overhead
• Manages large numbers of interrupts
The VIC offers high-performance, low-latency interrupt handling. The VIC prioritizes interrupts in
hardware and outputs information about the highest-priority pending interrupt. When external
interrupts occur in a system containing a VIC, the VIC determines the highest priority interrupt,
determines the source that is requesting service, computes the requested handler address (RHA), and
provides information, including the RHA, to the processor.
The VIC core contains the following interfaces:
• Up to 32 interrupt input ports per VIC core
• One Avalon
®
Memory-Mapped (Avalon-MM) slave interface to access the internal control status
registers (CSR)
• One Avalon Streaming (Avalon-ST) interface output interface to pass information about the selected
interrupt
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