Pci lite core, Core overview, Performance and resource utilization – Altera Embedded Peripherals IP User Manual
Page 135: Pci lite core -1, Core overview -1, Performance and resource utilization -1
PCI Lite Core
14
2014.24.07
UG-01085
Core Overview
The PCI Lite core is a protocol interface that translates PCI transactions to Avalon
®
Memory-Mapped
(Avalon-MM) transactions with low latency and high throughput. The PCI Lite core uses the PCI-Avalon
bridge to connect the PCI bus to the interconnect fabric, allowing you to easily create simple PCI systems
that include one or more SOPC Builder components. This core has the following features:
• PCI complexities, such as retry and disconnect are handled by the PCI/Avalon Bridge logic and
transparent to the user
• Run-time configurable (dynamic) Avalon-to-PCI address translation
• Separate Avalon Memory-Mapped (Avalon-MM) slave ports for PCI bus access (PBA) and control
register access (CRA)
• Support for Avalon-MM burst mode
• Common PCI and Avalon clock domains
• Option to increase PCI read performance by increasing the number of pending reads and maximum
read burst size.
Performance and Resource Utilization
This section lists the resource utilization and performance data for supported devices when operating in
the PCI Target-Only, and PCI Master/Target device modes for each of the application-specific
performance settings.
The estimates are obtained by compiling the core using the Quartus
®
II software. Performance results
vary depending on the parameters that you specify for the system module.
The table below shows the resource utilization and performance data for a Stratix
®
III device
(EP3SE50F780C2). The performance of the MegaCore function in the Stratix IV family is similar to the
Stratix III family.
Table 14-1: Memory Utilization and Performance Data for the Stratix III Family
PCI
Device
Mode
PCI Target
PCI Master
Logic
Register
M9K Memory
Blocks
I/O Pins
Enabled
N/A
715
517
2
48
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