Altera Embedded Peripherals IP - Manual (Page 232)

DMA Controller Core
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Core Overview
The direct memory access (DMA) controller core with Avalon ® interface performs bulk data transfers,
reading data from a source address range and writing the data to a different address range. An Avalon
Memor-Mapped (Avalon-MM) master peripheral, such as a CPU, can offload memory transfer tasks to
the DMA controller. While the DMA controller performs memory transfers, the master is free to perform
other tasks in parallel.
The DMA controller transfers data as efficiently as possible, reading and writing data at the maximum
pace allowed by the source or destination. The DMA controller is capable of performing Avalon transfers
with flow control, enabling it to automatically transfer data to or from a slow peripheral with flow control
(for example, UART), at the maximum pace allowed by the peripheral.
Instantiating the DMA controller in Qsys creates one slave port and two master ports. You must specify
which slave peripherals can be accessed by the read and write master ports. Likewise, you must specify
which other master peripheral(s) can access the DMA control port and initiate DMA transactions. The
DMA controller does not export any signals to the top level of the system module.
For the Nios
® II processor, device drivers are provided in the HAL system library. See the Software
Programming Model section for details of HAL support.
Functional Description
You can use the DMA controller to perform data transfers from a source address-space to a destination
address-space. The controller has no concept of endianness and does not interpret the payload data. The
concept of endianness only applies to a master that interprets payload data.
The source and destination may be either an Avalon-MM slave peripheral (for example, a constant
address) or an address range in memory. The DMA controller can be used in conjunction with
peripherals with flow control, which allows data transactions of fixed or variable length. The DMA
controller can signal an interrupt request (IRQ) when a DMA transaction completes. A transaction is a
sequence of one or more Avalon transfers initiated by the DMA controller core.
The DMA controller has two Avalon-MM master ports—a master read port and a master write port—and
one Avalon-MM slave port for controlling the DMA as shown in the figure below.
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