Altera Embedded Peripherals IP User Manual
Page 226
The control field is available for both the standard and extended descriptor formats. This field can be
programmed to configure parked descriptors, error handling and interrupt masks. The interrupt masks
are programmed into the descriptor so that interrupt enables can be unique for each transfer.
Table 22-3: Descriptor Control Field Bit Definition
Bit
Sub-Field Name
Definition
31
Go
Used to commit all the descriptor
information into the descriptor FIFO.
As the host writes different fields in
the descriptor, FIFO byte enables are
asserted to transfer the write data to
appropriate byte locations in the
FIFO.
However, the data written is not
committed until the go bit has been
written.
As a result, ensure that the
go
bit is
the last bit written for each
descriptor.
Writing '1' to the
go
bit commits the
entire descriptor into the descriptor
FIFO(s).
30:25
<reserved>
24
Early done enable
Used to hide the latency between read
descriptors.
When the read master is set, it does
not wait for pending reads to return
before requesting another descriptor.
Typically this bit is set for all descrip‐
tors except the last one. This bit is
most effective for hiding high read
latency. For example, it reads from
SDRAM, PCIe, and SRIO.
22-10
Control Field
UG-01085
2014.24.07
Altera Corporation
Altera Modular Scatter-Gather DMA