altera_avalon_mailbox_post()..................................................................................................... 27-6
Document Revision History.....................................................................................................................27-6
Vectored Interrupt Controller Core................................................................. 28-1
Core Overview............................................................................................................................................28-1
Functional Description............................................................................................................................. 28-3
External Interfaces......................................................................................................................... 28-3
Functional Blocks...........................................................................................................................28-4
Register Maps............................................................................................................................................. 28-6
Parameters................................................................................................................................................ 28-11
Altera HAL Software Programming Model.........................................................................................28-11
Software Files................................................................................................................................28-11
Macros...........................................................................................................................................28-12
Data Structure.............................................................................................................................. 28-13
VIC API.........................................................................................................................................28-13
Run-time Initialization................................................................................................................28-16
Board Support Package...............................................................................................................28-16
Document Revision History...................................................................................................................28-23
Avalon-ST JTAG Interface Core....................................................................... 29-1
Functional Description............................................................................................................................. 29-1
Interfaces.........................................................................................................................................29-1
Core Behavior.................................................................................................................................29-2
Parameters...................................................................................................................................... 29-3
Document Revision History.....................................................................................................................29-3
System ID Core..................................................................................................30-1
Core Overview............................................................................................................................................30-1
Functional Description............................................................................................................................. 30-1
Configuration............................................................................................................................................. 30-2
Software Programming Model.................................................................................................................30-2
alt_avalon_sysid_test()..................................................................................................................30-2
Document Revision History.....................................................................................................................30-3
Performance Counter Core...............................................................................31-1
Core Overview............................................................................................................................................31-1
Functional Description............................................................................................................................. 31-1
Section Counters............................................................................................................................31-1
Global Counter...............................................................................................................................31-2
Register Map...................................................................................................................................31-2
System Reset................................................................................................................................... 31-3
Configuration............................................................................................................................................. 31-3
Define Counters............................................................................................................................. 31-3
Multiple Clock Domain Considerations.....................................................................................31-3
Hardware Simulation Considerations.................................................................................................... 31-3
TOC-11
Altera Corporation
