Altera Embedded Peripherals IP - Manual (Page 75)

accept another character, and to read data only when the core has data available. The UART core can also
optionally include the end-of-packet register.
Include End-of-Packet Register
When this setting is on, the UART core includes:
• A 7-, 8-, or 9-bit
endofpacket
register at address-offset 5. The data width is determined by the Data
Bits setting.
• EOP bit in the
status
register.
• IEOP bit in the
control
register.
•
endofpacket
signal in the Avalon-MM interface to support data transfers with flow control to and
from other master peripherals in the system.
End-of-packet (EOP) detection allows the UART core to terminate a data transaction with an Avalon-
MM master with flow control. EOP detection can be used with a DMA controller, for example, to
implement a UART that automatically writes received characters to memory until a specified character
is encountered in the incoming RXD stream. The terminating (EOP) character's value is determined
by the
endofpacket
register.
When the EOP register is disabled, the UART core does not include the EOP resources. Writing to the
endofpacket
register has no effect, and reading produces an undefined value.
Simulation Settings
When the UART core's logic is generated, a simulation model is also created. The simulation model offers
features to simplify and accelerate simulation of systems that use the UART core. Changes to the
simulation settings do not affect the behavior of the UART core in hardware; the settings affect only
functional simulation.
For examples of how to use the following settings to simulate Nios II systems, refer to
AN 351:
Simulating Nios II Embedded Processor Designs .
Simulated RXD-Input Character Stream
You can enter a character stream that is simulated entering the
RXD
port upon simulated system reset. The
UART core's MegaWizard ™ interface accepts an arbitrary character string, which is later incorporated
into the UART simulation model. After reset in reset, the string is input into the
RXD
port character-by-
character as the core is able to accept new data.
Prepare Interactive Windows
At system generation time, the UART core generator can create ModelSim macros that facilitate interac‐
tion with the UART model during simulation. You can turn on the following options:
• Create ModelSim alias to open streaming output window to create a ModelSim macro that opens a
window to display all output from the
TXD
port.
• Create ModelSim alias to open interactive stimulus window to create a ModelSim macro that opens
a window to accept stimulus for the
RXD
port. The window sends any characters typed in the window
to the
RXD
port.
Simulated Transmitter Baud Rate
RS-232 transmission rates are often slower than any other process in the system, and it is seldom useful to
simulate the functional model at the true baud rate. For example, at 115,200 bps, it typically takes
thousands of clock cycles to transfer a single character. The UART simulation model has the ability to run
with a constant clock divisor of 2, allowing the simulated UART to transfer bits at half the system clock
8-6 Simulation Settings
UG-01085
2014.24.07
Altera Corporation UART Core
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